IP Soft Core Design Of UART Supporting IRDA1.0

According to the anxious requirement of the information technology and the wide application of data communication, IP soft core of UART supporting IRDA 1.0 protocol is designed. And it not only can be applied as a module, but also can be widely applied in system level chip design. The design of IP core is the most practically useful and referential for developing and perfecting IP core store in our country. Moreover, The IP soft core has a large economic market.The project use "Top_down" technology to develop core by dividing UART according to it's function. At first .design and simulate on single module, secondly, on the whole system, at last verification using FPGA. The result proved the design is reliable and perfect on function.There are six sections in the whole thesis. The third .fourth, and fifth sections are emphases of the project, these sections mainly describe how to design the IP soft core.The first section, the necessity of designing the IP soft core of UART supporting IRDA 1.0 protocol is discussed by analyzing the actuality of the 1C development and the application of the data communication technology ,and prove that it has science and economy significance .The second section, the principle of UART and IRDA1.0 protocol is analyzed deeply.The third section, how to design is introduced according to the idea of the design .At first, the function index is introduced. Secondly, the different function and mode of UART is introduced too. At last, how to divide the UART and how to design the single module are introduced.The fourth section, the last simulation charts are given to prove the right of design.The fifth section, the whole process of FPGA verification is introduced particually. The whole system is designed according to the design flow. The main process includes following: system design, module design , function simulation, time simulation and hardware verification. The whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of UART and the requirement of design. The module design is to design inner circuit structure of each module and uses Verilog language to code the code. The functional and time stimulation uses the NC-Verilog of Cadence. First, each module is simulated. Then, after the right result comes out, the code of each module is assembled to form the code of whole system. Last, the simulation signal is applied on outer port to simulate the whole system. FPGA is used to verify the function of the system. The FPGA chip used is XC2S50PQ208 of Xilinx. The configure file is downloaded into the FPGA chip according to the FPGA design flow. Also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. And the logical analyzer is used to sampling the output signals. The results of test show that the design accomplished the requirements perfectly.The six section, sum up the works , harvest and what one has learned. And give a future view about the project.