Multi-power Supply Network Design For SoCs

With the improvement of the manufacturing process, the metal wire width decreases and thetotal length of wire is increasing, this trend makes wire resistance of the power network increase,and with the process of scaling, lower supply voltage and the power of the network connectionvoltage drop caused by resistance, making the supply voltage can not meet the requirements,resulting in chip logic error, or even burning chips. Therefore, the power distribution networkanalysis and design optimization is to ensure correct operation of the circuit. Traditional powernetwork analysis methods are mainly applied at the transistor level and post-layout verification. If aproblem occurs, it has to return the first stage to improve the analysis process, which not onlycomplexes the process but also is very time-consuming. In this dissertion, combining the structuralfeatures of SoC, the current SoC floorplanning and power network research situation are described.In order to achieve rapid completion of the entire design process, floorplanning and multi-powersupply network co-design methodology is proposed, the power supply network voltage dropanalysis step is integrated into floorplanning stage, to achieve the rapid completion of the entiredesign purposes. These design methods have been verified in the MCNC benchmark circuits. Thedissertation is composed of the following sections:1. Aiming at the traditional floorplanning method, based on the optimize the SoC module area,wire length, using a compact temperature model, successful introduction of the temperature factor,the floorplanning problem is modeled as a combinatorial optimization problem by simulatedannealing algorithm to minimize the module area, wire length and temperature of the target,experimental results show that the proposed algorithm can effectively reduce the moduletemperature.2. Given the matrix in MNA is not sparse positive definite, there is no advantage on theprocess of matrix inversion in time and precision. In this paper, we presents an improved method,the voltage source node to the node known as MNA equations, making only a conductance matrixequation on the left, not with the other matrix, the conductivity matrix is then Choleskydecomposed and the node voltage is obtained without the process of matrix inversion.3. Against SoC traditional design flow problems, a floorplanning and multi-power supplynetwork co-design methodology is proposed. While adjusting the floorplan and multi-powersupply network structure, the optimal solution can be obtained, which can improve the P&R and entire chip design process efficiency. Experimental results show that not only the floorplan can beoptimized, but also the voltage drop and routing area can be effectively reduced.