Research On Moving Target Detection System Based On FPGA And Machine View

With the development of computer technique, digital video technology has a widerange of application in these fields such as industrial production,security monitoring,consumer electronics,intelligent transportation and so on. And on that basis, a newtechnology-Target tracking is developed which is used to realize artificial intelligencemachine vision and has a larger application prospect in the domains like visionmanipulator achieved,line work piece sorted,defect product testing,vehicle tracking.At present, moving target tracking technology implemented with ARM﹑DSP orPC becomes a problem for its large amount of data,complex algorithm and highstability. Along with all kinds of high quality video developed and compressed formatcontinuously improved, operation speed of image processing system becomes higherand higher and its real-time,parallel,stability is difficult to meet. However, FPGA willgradually show the advantages such as high speed,low developing difficulty,wellreconstruction and low cost, and compete with others.In the study, the CMOS camera is adopted to high-speed collect image informationand NiosII soft IP core of Altera FPGA is used to process image which can get the size,location and the information of the target, and then drives servo steering gear tripodhead to make the camera to track the target and also can realize VGA displayed.Moving target tracking system includes camera driving module,video acquisitionmodule,the video input buffer FIFO,SOPC system,steering gear PWM controlmodule,video output buffer FIFO,VGA display interface module. Camera drivingmodule uses Verilog HDL language to implement SCCB bus timing and configurateCMOS camera initially. Video acquisition module also uses Verilog HDL language toconvert video format, which will transform a serial of8bit RGB565data into a parallel16bit RGB565data, and produce data effective signal. Input/output buffer FIFO isbased on FPGA own IP cole generation to make asynchronous clock to synchronize.VGA module is used to make the image of SDRAM to display to VGA displayer onreal-time. PWM module is responsible for driving the target information by calculatedto steering gear tripod head. The SOPC system includes NiosII processor, Avalon bus,DMA controller, SDRAM controller, and custom FIFO controller. Among them thedata transmitted from FIFO to SDRAM is adopted by DMA mode, in order to reducethe load of NiosII processor.The architecture of system finishes in QuartusII, the system algorithm designs anddebugs in NiosII IDE integrated development environment using C language, whichmainly includes the system bottom driver program and the upper applicationdevelopment. Finally, through the Modelsim function and timing simulation, QuartusIIis used to the line synthesis and locating and wiring to the whole system engineering.The configuration files are downloaded to FPGA when the sequential analysis reportmeet the requirements.The experimental result shows that the design of the system meets expected requirement, and has the good performance in real time and accuracy, and lay thefoundation for the further development.