Design And Implementation Of Moving Target Detection System Based On SOPC

In recent years, with the rapid development and improvement of computer technology and digital image processing technology, as well as the in-depth research in the fields of intelligent video surveillance system, robot navigation, traffic detection and video image compression and so on, moving target detection is paid more attention. The SOPC system based on FPGA can meet the needs of high speed image processing. The use of FPGA can take full advantage of parallelism of hardware and improve the speed of image processing in essence so that image processing with the large amount of data can achieve real-time ability. SOPC technology can make the design flexible, trimmed, scalable and upgradeable. Besides, software and hardware in-system are programmable.This paper designs a moving target detection system based on SOPC. The system uses DE2 development board of Altera as the hardware platform. CMOS image sensor monitors the environment in real time. VGA displays the monitoring environment. When moving targets come into the environment, headphones and LEDG2 of DE2 development board send the alarming signal to notify the monitoring staff.Using a synergistic manner through software and hardware, the entire system is realized. Hardware:first of all, on the basis of the requirement analysis, the paper designs and implements all the modules, including image capture module, SDRAM module, image display module and DC2 module; and then, the paper builds DC2 module using SOPC Builder; finally, the thesis builds the entire hardware system by Quartus II. Algorithm:the paper adopts three algorithms to detect moving target, including frame substraction algorithm, edge area based on absolute difference moving detection algorithm and erosion and expansion algorithm, so that the detected result can be more accurate. Software:the algorithms are programmed and debugged by C code in the Nios II IDE environment. Moreover, the thesis optimizes Nios II software code and uses Nios II C2H compiler to accelerate hardware processing. After a period of debugging and running, the system realizes the expected results.