The Development Of Software Radio Transceiver Dbf Radar System Circuit

Software defined radio (SDR) technique has lots of excellent features, such as versatility, flexibility, openness and has already been widely used in wireless communication, radar, electronic warfare and other fields. The main idea of SDR is to construct an open, standardized, modular generalized hardware platform, and leaves various functions implemented in software as much as possible. In this thesis, in order to meet the demands of the DBF radar system, a ten-channel IF transmitter-receiver SDR circuit has been designed and developed. The main work of this thesis is the hardware and software design of the circuit, including schematic design, PCB design, interface program debugging, performance testing and system function realization. The circuit designed in this thesis has been used in the DBF radar system and satisfy the requirements of system requirement. The main features of the ten-channel IF transmitter-receiver SDR circuit include:1. High-speed data sampling capability. Ten ADC channels are integrated in the circuit. The highest sampling rate of the ADC chips is 125MSPS, using source-synchronous technology to achieve high-speed data transmission. The actual sampling rate of the circuit achieved is 100MSPS with ENOB up to 9.4.2. High-speed digital-to-analog converting capability. Ten DAC channels are integrated in the circuit. The highest sampling rate of the DAC chips is 500MSPS, using parallel differential signal bus to achieve high-speed data transmission. The actual sampling rate using in the circuit is 250MSPS, and the phase noise of the ciruit is less than-120dB/Hz in the bandwidth of 1kHz (IF 30MHz) and the spurious free dynamic range is more than 60dBFS.3. High-speed fiber data transmission capability. Two fiber modules have been integrated in the circuit for serial high-speed bi-direction data communication with data rate up to 3.125Gbps, which satisfy the large data transmission requirements of DBF system.4. Powerful digital signal processing and storage capability. Virtex5 series FPGA has been used as the core signal processor, which achieves 10-channel digital down convert, 10-channel digital signal synthesis and signal pre-processing. Besides,64Mbit DDRII memory and 8Mbit flash memory have been integrated for data caching and non-volatile data storage.