Research Of The High-Speed Serial Interface And Traffic Control Technique For A Multi-net Gateway

The rapid development of Internet has a higher demand for the performance of network devices like the gateway. The traditional gateway implemented by using very large scale integration (VLSI) is lack of flexibility. Integrating excellent performance and high flexibility, the network processor becomes one of the best hardware candidates for constructing multi-net gateways. Traffic control is an important factor in determining the performance of communication links, networks and interconnected networks. So, it is of great significance in applications to study the traffic control technique based on network processor.On the basis of the project named"the research on the key techniques and prototype of a multi-net gateway", this dissertation first outlines the multi-net gateway, the hardware architecture and software framework of IXP2350 network processor, as well as traffic control techique.Secondly, one emphasis of this dissertation is on investigating the working principle of the high-speed serial interface (HSSI) on IXP2350 network processor and implements the function of this interface through programming. It also concentrates on the queue management and scheduling of traffic control technique, and puts forward an improved deficit weighted round-robin (DWRR) scheduling algorithm based on the study of original DWRR algorithm under DiffServ model. Meanwhile, traffic shapping is carried out in combination with the token bucket algorithm. This dissertation not only designs and implements traffic control system based on the IXP2350 network processor, including the functions and algorithms of each module in the traffic control system, but also fulfills performance simulation and function verification with the help of the simulation tool of workbench.