32Bit DCT/IDCT IP Soft Core Design

As technology continues to evolve into multimedia time, especially since the era of telecommunications, video and audio compression demand faster speed. In order to achieve high-quality high-speed audio and video compression and decompression, discrete cosine transform algorithms are increasingly being applied to the multimedia compression standard. Such as JPEG, MPEG1, MPEG4, H.264and other video standards, they have adopted the DCT transform compression algorithm. Due to the computational complexity of the process, software cannot meet the requirement, dedicated hardware circuits are needed to ensure compliance with requirements.IDCT is the reverse transform of the DCT. They have the same structure and algorithm, so this paper is based on the design for the two-dimensional DCT transform to study the DCT/IDCT transform theory and design methods. Firstly, the development of fast algorithms of DCT history and several different implementations, analysis of the advantages and disadvantages of various implementations, and algorithms used are introduced in this article. Then I introduced the FPGA and ASIC design process knowledge, as IP soft-core must be able to do that on a different platform can achieve can be integrated into the physical layout of the application form to get the job. At the beginning of the design I must first determine the design parameters, and here I use the C language to create the DCT calculation model to analyze the different parameters which affect the results for the operation, select the appropriate word length to meet the design requirements to avoid resource waste, so that the greatest optimization of the design can be achieved. After designing the parameters I finish the module design with Verilog language. At last, the soft core is implemented on both FPGA and full custom circuit to prove that the design module can be realized.The main findings of this paper are:1. Study the DCT calculation methods and different implementations.2. Study the FPGA and ASIC design flows.3. completed a two-dimensional DCT and soft-core design that can be applied.