Research And Implementation Of1024-point Pipeline FFT Algorithm Based On FPGA

With the development of digital electronic technology, digital signal processingtechnology has been widely applied in various fields, like communications, imageprocessing, radar and multimedia. As the core technology of digital signal processing,Fast Fourier Transform(FFT) reduces the computation time of Discrete FourierTransform(DFT) by several orders of magnitude, which makes digital signalprocessing much easier to implement and apply. So it is of great theoretical andpractical significance to research FFT algorithm and its implement.Based on the structure and the operational characteristics of FFT, this paperproposes a complete implementation method of1024-point,16-bit fixed-point complexFFT on the basis of field programmable gate array(FPGA). First, it discusses thetheoretical foundation and operational rules of Radix-2Decimation-In-Frequency FFTalgorithm. Then it discusses several different hardware architectures with butterflyflow graph of FFT algorithm. At last, it ascertains the pipeline structure to implementthe design considering system performance and resource consumption.The structure of the algorithm is designed according to the hierarchical top-downdesign method, and it is divided into several functional modules. These modules areimplemented in hard description language Verilog HDL based on the verificationplatform of XILINX Virtex-5FPGA. All functional modules are synthesized on theplatform of ISE integrated development environment and we get corresponding RTLhardware circuits.After the synthesis by ISE, the maximum frequency of the algorithm reaches250MHz. It costs2073clock cycles for one complete FFT processing, which satisfiesthe speed requirement of real-time signal processing. The code used to verify theaccuracy of the algorithm is fulfilled based on the fft function provided by MATLAB.Experiment results show that the designed algorithm achieves a certain accuracy thatsatisfies the request of common signal processing. The work done in the paper isvaluable for FPGA-based hardware implement of algorithms in the future research.