Research On Key Technologies Of Integrated DSP Module On Hign-Performance FPGA Chip

Since the appearance of Field Programmable Gate Array(FPGA),relying on its short design cycle and high flexibility,it has quickly become a typical representative of the integrated circuit chip industry.It has been used in the communication field,biological field,image video in high-speed computing applications such as fields.With the development of the information age,the demand for FPGA in popular areas such as deep learning heterogeneous acceleration and artificial intelligence is also increasing.With the development of semiconductor technology and microelectronics industry,FPGA integration scale has reached a new height,and embedded DSP hard core as the main device of digital signal processing has received more and more attention.The speed of the DSP hard core is related to the performance of the FPGA chip.Therefore,it is particularly important to improve the performance of the DSP hard core.Aiming at the function and performance requirements of the domestic FPGA platform for the DSP module,this thesis focuses on the design of the core multiplier and related algorithm module in the FPGA-based DSP module.Through the design analysis of its internal modules,using foreign related products and data manuals,the relationship between configuration data and circuits is grasped.Understand the module design structure,function and principle,refer to the overall architecture design of the existing embedded DSP hard core,and plan the overall architecture of the module.First,compare multiple multiplier algorithms,choose the improved base4 booth coding and Wallace tree structure for partial product generation and compression,and improve the compressor required by the Wallace tree structure.After partial product compression form two sets of data.In this design,the partial product summation circuit and the adder circuit are combined into one,and a three-input adder can be designed to meet the demand.The mixed structure of the carry-select adder and the super-advanced adder is used.The multi-channel selection structure combined with the three-input adder enables the DSP module to complete functions such as multiply-add,accumulate,and cascade.The innovation of this thesis is to complete the unification of signed numbers and unsigned numbers,simplify the calculation of the symbol array,and reduce the number of compressors used.The compressor circuit used in the partial product compression circuit adopts a symmetrical structure,which reduces the skew of the signal,and the generated signal does not need to be synchronized again.Increasing the stability of the circuit has a positive effect on optimizing the timing of the circuit structure.Analyze the characteristics of 6-3 compressor and 7-3 compressor and simplify the circuit.The multiplier is determined to be 25 bit × 18 bit based on the design frequency requirement and the bit width limitation of the adder.A functional verification platform was built during the design process to conduct preliminary verification of the functions of the DSP module.After the module design was completed,in order to further ensure the correctness of the design,a coverage simulation was carried out.The UVM verification platform was built using the System Verilog verification language,and the coverage simulation of the module was performed,and the coverage reached 97.27%.Use analog simulation to simulate the parameters,and select the longest delay path to test the highest frequency of the circuit.Finally,the tape-out and the test of the real film are completed.