Related Technology Research On The Architecture-level Power Model Of Microprocessors In Deep Sub-micron Technology

With the sustainable development of semiconductor technology and the significant increment of chip integration, heat of chips keeps increasing while reliability keeps declining. It limits further improvements of performance, making power a key issue in the microprocessor design area. Power simulations in early stages of microprocessor design can help to find problems and constrains in designs. It is an effective aid to the selections and improvements of designs.There are already some ripe models and simulation tools for power evaluation. Such as EDA tool SpyGlasses, dynamic power simulator Wattch, leakage power simulator HotLeakage and CACTI, a power simulator for storage structures. However, general low-level simulation tools are expensive, and therefore are not suitable for architectural researches. The classic architecture-level simulation tools usually cannot reflect the latest changes in structures and processes. Furthermore, they are not able to evaluate the actual power of microprocessors in different application scenarios.This paper puts forward new power models of microprocessors, including dynamic power model SMPD and leakage power model SMPL. SMPD is a dynamic power model of microprocessors under deep sub-micron technology. It can be used to estimate the dynamic power of microprocessors'components with different configurations statically. Similarly, SMPL is a leakage power model of microprocessors under deep sub-micron technology. It can be used to acquire leakage power estimations statically. SMPD and SMPL models are based on up-to-the-minute micro-architectures and processes, leading to a more accurate power estimation for modern microprocessors. In addition, a new method has been proposed in this paper to improve computing speed of the SMPL model.On the basis of the above two models, a new dynamic power simulation model which is called SMP is established. As the power model of the whole microprocessor, it can integrate different architecture-level simulators to get dynamic and leakage power estimations of microprocessors with different architectures. Also, SMP model can run the actual applications, which is a huge difference from SMPD and SMPL model. Therefore, its simulations results not only reflect the structural and process's characteristics of microprocessors, but also the characteristics of application scenarios. Finally, a design space exploration is carried out with the SMP model.The research work in this paper has established the foundation of microprocessors'architecture-level power evaluation. Some of the considerations and arts is of great value to researchs on low-power design and power optimization.