Architectural Level Leakage Power Optimization For Ultra-Deep Submicron Microprocessors

High performance has always been the main object in microprocessor design, but at the same time power issue in ICs becomes challenging and needs special care. Specially, leakage power will exceed dynamic power as feature size shrinks in the next several generations. The exponential increase of microprocessor frequency will cease and even the chips will corrupt due to the limit of heat sinks if leakage power is out of control. Furthermore a great deal of energy will be consumed in vain even if the circuits are idle.As leakage power gets more and more severe, only process-level and circuit-level low power technologies can not meet our expectation. Leakage power warrants architectural effort to take care of it. How to aggressively reduce leakage power without impacting processor performance is the main concern to architects.An overview of current architectural level low leakage power design techniques is made. Two basic ideas are summarized. One is to reduce transistors which are idle but leaky. And the other is to preferentially cool the hotspots on chips, such as memory structures, through controlling their active rates. To trade off between performance and power, leakage-power-oriented simulation framework and evaluation system are needed. Detailed researches have been done on the above issues. The main contributions are as follows:1. The advantages of archtectrual level leakage power control are analyzed and related work is discussed. Several special techniques are detailed and their advantages and disadvantages are illustrated.2. The architectural level leakage model and power simulator are analyzed. An experimental framework is established for the development of leakage power control policies. A new leakage power oriented evaluation system is also proposed to show the efficiency of power reduction, performance protection and performance-power tradeoff.3. According to the analysis of on-chip secondary cache behavior, ADSR (Always Drowsy Speculatively Recover), a new architectural algorithm for leakage power controlling based on state-preserving low leak SRAM circuits, is proposed. All cache lines are put into low leak mode by default, and prefetching-like prediction NLP+SBP mechanism is used to speculatively recover cachelines for hiding wakeup latency.4. According to the analysis of on-chip data cache behavior, LRU-assist algorithm is proposed, using existing LRU information to more aggressively cutting cache lines off besides the effect of traditional cache decay with hierarchical counters. Same as LRU-assist, a "logical way" granularity resizable cache is shown to compare with other granularity resizing.5. According to the analysis of on-chip instruction cache behavior, based on state-preserving low leak SRAM circuits, PDSR (Periodically Drowsy Specula- tively Recover) mechanism is proposed to drowse cache lines without severe performance loss. An extension to PDSR, adaptive PDSR (APDSR) is developed to improve the efficiency dithering in PDSR across a wide range of benchmarks.6. According to the analysis of branch predictors on chip, a synchronous algorithm with instruction cache base on state-preserving SRAM circuits is proposed to control the leakage power of BHT, PHT and BTB structures. A noaccess algorithm based on state-destroying circuits is also proposed for separate BHT, PHT and BTB design.Plenty of experiments are made. Results show that all the proposed architectural leakage power optimization mechanisms can achieve aggressive power saving without obvious performance reduction. The evaluation system can also evaluate control policies fairly and accurately when power and performance tradeoff is needed.