UPF Low Power Methodology In Super Deep Submicron Technology

In recent years, the rapid development of hand held devices such as cell phonesand tablets makes the speed and ability of mobility chips improving extremely fast.High performance computing and multi-media processing require much more powerconsumption. Nanoscale CMOS technology, from65nm on, poses a problem that thestatic power is as bigger as the dynamic power. Low power design must be added intothe design flow to properly create a power grid to reduce the static power as well asdynamic power.Based on TSMC28nm CMOS technology, the thesis takes a digital basebandchip’s power grid design as the object of research, and gives the method of power intentdesign and verification based on UPF low power methodology. It also does the researchof power control sequence development and power up pre-charging techniques.The thesis is used Modelsim Power Aware Simulation to verify UPF power intentmatching the RTL design. The test method and simulation waveform is given. The lowpower methodology in this thesis comes from the real practice of low power design. Itcan be a good reference.