Deep Submicron Integrated Circuits, Low-power Design

With the descending of the process characteristic size, IC had improved greatly on the aspects of integration and performance. However with the improvement of the system complexity and the wide application of various mobile equipments, power consumption become an important bottleneck of chip design development. Power consumption not only affects chip package type and cost, also causes the increase of chip temperature, which will decide the reliability of chip directly. The increase of system power will bring about the issues on electron-mobility effect and increase in current density, resulting in the deterioration of chip stability. Furthermore, these phenomena will bring multitude of challenges into the design of power supply and analysis of circuit reliability. The research of low power technology is becoming more and more imminent. All these factors will force the designers to focus more and more research of evaluation and optimization on IC power consumption.This paper initially discusses the research background on the deep sub-micro low power chip design . Then the paper summarizes the fundamental research content of the most current SoC low power technology and mainstream low power design technology. This paper places latter emphasis on several low power techniques on standard cells, such as level shifter for multiple power supply, flip-flop with data retention capability, and back-bias technology.