Design And Implementation Of Power Management System In Low-power Microprocessor

Since the beginning of the 21 st century,with the rapid development of the information industry,such as consumer electronics,automotive electronics,sports health,smart home and other emerging fields have sprung up,bringing an endless stream of intelligent,information-based products.These changes have brought new vitality and vitality to the microprocessor,a traditional control device,whose market demand is rising year by year.At the same time,the market also puts forward a new demand for microprocessors: low power consumption index,and with the development of the market,this index is not the lowest,only lower.Low power consumption has become the main trend of microprocessor development and an important goal of microprocessor design.In this context,this paper studies the power management system for power management in microprocessor.Firstly,this paper starts from the application scenarios of microprocessor,analyzes the characteristics of different application scenarios,and completes the multi-mode design based on ladder power management.The microprocessor is divided into four configurable working modes with different performance and power consumption.On this basis,combined with the overall structure of the microprocessor,the design and implementation scheme of the power management system is proposed.The power network of the microprocessor is designed by using multi power domain,power gating and other technologies,By using LDO with different performance in the working mode and stop mode to optimize the power performance in the low power consumption mode,the power management module is designed to realize the all-round control of the system state change and power signal.For the clock signal in the system,this paper designs a tree structure clock network,and uses the clock management module to manage all clock gating and clock frequency division.At the same time,aiming at the problem of long wake-up time caused by the low clock frequency of the power management module,a simple logic clock switching circuit is designed,The clock source of the power management module is switched in different states to improve the effective running speed of the microprocessor.According to the hardware and software co-verification strategy,this paper conducts a complete functional verification of the microprocessor and power management system,and demonstrates the correctness of the design.The final chip return power test results show that the power consumption of the microprocessor is22 ua / MHz in the normal working mode,1.8ua in the stop mode and 50 na in the standby mode,and there is an obvious power gradient between each mode,Compared with other low-power types of microprocessors,we can see that the low-power index of the microprocessor in this paper is close to or has reached the most advanced level in the market,which proves that the designed power management system has a good low-power optimization effect.