Design And Achievement Of Radar Digital Receiver Based On SOPC

With the rapid development of digital technology, digital signal processing has become the core of a variety of functions in modern radar applications. It is an important prerequisite of digital signal processing to realize a reliable radar signal receiver because radar echo signal is always analog signal.An embedded dual-channel digital receiver is designed using the idea of hardware and software co-design based on SOPC technology. The digital receiver employing FPGA as the main control chip, DDR2 SDRAM as buffers, CPCI bus as system bus, can complete dual radar signal high speed acquisition, down-conversion processing,real-time storage and transmission. The content of this research includes the following aspects:Firstly, the related theories on digital receiver are introduced. Based on the analysis of the performance parameters of instantaneous polarization radar digital receiver, the overall design of digital receivers and the signal processing simulation are given. The key technologies involved include the design of digital mixer, digital filter and digital decimation filter.Secondly, the overall system hardware design is given based on the digital receiver design, and each function module hardware design is introduced in detail. Embedded control based on SOPC technology is employed as the system control scheme. The IP CORE used for acquisition control, digital down-conversion and CPCI interface are designed while their drivers are compiled. The hardware platform based on Microblaze is built, and the control flow of the system is designed.Finally, channel inconsistency in dual-channel receiver system is analyzed, and a balanced program which is proved to be effective is given. System functionality and performance is tested, and the test results are given.Test results show that the system can complete the radar signal acquisition, down-conversion preprocessing, caching and transmission functions, and achieves the desired performance.