Font Size: a A A

Research On APP-Based Decoding Algorithm For Low-Density Parity Check Codes And The Hardware Implementaion Of Full-Parallel Decoder

Posted on:2012-07-11Degree:MasterType:Thesis
Country:ChinaCandidate:X R WangFull Text:PDF
GTID:2218330362951660Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Low-Density parity-check (LDPC) codes, first proposed by Gallager, are proved to achieve near Shannon limit error performance and represent a very promising prospect for error control coding. With its low decding complexity, and the feasibility of parallel hardware implementation, LDPC codes are most likely to become the key technoque of the fourth generation of mobile communications.In this paper, the decoding algorithms and the hardware implementation of parallel decoder is studied. The main researches are described as follows.First, the decoding algorithms for LDPC codes are investigated, including both the hard-decision algorithms and soft-decision algorithms. On aspect of hard-decision algorithms, the BF(Bit Flipping) and WBF(Weighted Bit Flipping) algorithms are introduced. For the soft-decision algorithms, the BP(Belief Propagation), LLR BP(Log Likelihoood BP), APP(a posteriori probability), BP-Based, APP-Based and the performance-improved algorithms, i.e. Normalized and Offset algorithms, are described.Secondly, a modified APP-Based decoding algorithm is proposed. The modified APP-based algorithm utilizes an additional processing in the bit nodes to improve the accuracy instead of the check nodes normalization performed in normalized APP-based algorithm. The modified APP-based algorithm yields desirable trade-off between performance and decoding complexity.In the last, the structure of a parallel decoder with high throughput rate for decoding irregular LDPC codes by the proposed modified APP-Based algorithm is implemented. A series of simualtions are conducted to obtain the optimum value of supress factor of the algorithm for fixed bit width. Each module of the decoder is analyzed and implemented using Verilog HDL under the ModelSim 6.5 environment. The hardware implementation of the decoder is verified and estimated by Synopsys Design Vision and Xilinx ISE 13.1. The speed, power and area reports are given in this paper.
Keywords/Search Tags:Low-density parity-check (LDPC) codes, APP-based decoding algorithm, parallel decoder
PDF Full Text Request
Related items