Multiple-Bit Upset Tolerant SRAM Design Based On RS Codes

With the decrease of technology, more and more transistors are integrated in one chip, hence the probability of MBUs in aerospace electronic devices is becoming higher and higher. These electronic devices include many storage cells and combinational circuits such as adder. Both these circuits are prone to MBUs. However, the structure of storage cell is more susceptible to MBUs.Hence, it is necessity to adopt some methods to reduce the effect of MBUs to memories and improve the reliability of electronic devices.Error Correction Codes are effective approaches to correct multiple bits errors in systemtic level.Compared to methods in devices level,circuit level and layout level, this method doesn't need to change the mask parameters and it is easy to implement in circuits.Besides it can decrease the cost. However, Hamming codes are able to correct only single bit error, they are not enough to provide required reliability with the increasing density of transistor and the probability of MBUs. Therefore multiple error correction codes are necessity.In this paper, RS codes which are block-base and capable of correcting multiple bits errors are used to protect SRAM against MBUs.Many multiplication operations are needed in the process of RS codes encoding and decoding.The normal method adopts look-up table to implement the multiplication which will bring much area and power overhead and increase the circuit complexity.A novel multiplication matrix is proposed and used in encoder and decoder to replace the look-up table.The implement resuls show that using the product matrix the area of encoder and decoder are decreased significantly. Moreover the generic method to construct product matrix is given in detail.Besides novel parallel decoding algorithm is used in decoding process which can complere the operation in one cycle and is easy to implement in hardware.At last, the modeling and simulation for encoder and decoder in RTL level are completed using Verilog HDL. A set of experiments is used to assess the error correction capability of SRAM. From the results it is obvious that RS codes can correct multiple bits errors with low area and power and achieve higher reliability.