Design Ldpc Codes For Multiple Bit Upsets Mitigation In Sram

As integrate circuit is becoming complex and its ability of dealing with data is changing more and more power, The proportion of SRAM is also greater than that of before, the number of SET in combinational logic circuit is close to that of SEU. As a result, efficient eliminating soft error and circuit hardening techniques for SRAM are paid more and more attention.Through studying the structures of Euclidean geometry and low density Parity check code, we make a design which is also called EG_LDPC, it is could be used to harden SRAM. This design is different form the common code. There is parallel Majority Logic decoder and feedback-ring in this design, because of them the code is not only can avoid the SEU in memory array, but also can eliminate the SET which is taking place in its encoder and decoder.The EG_LDPC is a one or more step majority logic code, we propound a arithmetic which can limit the number of the majority logic decoder's steps to two, because of this the speed of decoder is upgraded greater. And we further introduce curtate EG_LDPC code whose information bites can be altered randomly but keeping the original ability of correcting errors. When analyzing the reliability of the system we also introduce a means to count the MTTF of the hardened system which is definitude and simple.After the functions of all kinds of modules are validated, we also analyze performance and reliability of EG_LDPC code through error-inject experiment. We also make a contrast with other codes including Hamming code Matrix code and Reed-Muller code. The result indicate that EG_LDPC code can achieve higher reliability with a little more area delay and energy overhead than the other codes, the MTTF of EG_LDPC code is indeed 3.19 times than that of Hamming code.