Multiple-bit Upset Tolerant CAM Design Based On Built-in Current Sensor

As technology scales, the probability of multiple bit upsets (MBUs) in memory gets greater, becoming an important factor of the reliability in memory. Content-Addressable Memory is a special kind of memory, besides of normal reading and writing function, it can search for all memory in a cycle, and giving the address of the searching data; Commonly used in the search intensive areas , such as cache, lookup table in route and so on. Using SRAM cell as memory cell core, but have big ground bounce noise, make CAM more vulnerable to the impact of soft errors, so it has great significance to study the MBUs hardened technology of CAM.For the special structure, it's not suitable to directly use of ECC for CAM. In this paper, we take the think of current sensor, propose a method to address the MBUs in CAM, which using Built in current sensor (BICS) to detect and locate the column of errors, using multiple-bit parity codes to locate the row of errors. Combine error correction circuit and read /write control circuit to complete correction action.In this paper, first we design a 64x64 bits conventional CAM, then we finished the design of BICS circuit,encoder and decoder circuit,error correction circuit respectively, finally combine all the sub circuit, we designed a 64x64bit CAM according to the proposed method , verified and analysis the designed CAM, The simulation result show that proposed method can detect and correct 4 bits errors in CAM, detect time is about 1.1 ns. We designed the layout of the main circuits at 0.18μm process, design result show that proposed method has less than 13% area overhead, achieve the aim of hardened CAM design at lower costs of performance and aera.