Performance analysis of computation speedup in delay-insensitive dual rail logic circuits |
Posted on:2001-07-04 | Degree:M.S | Type:Thesis |
University:Texas A&M University - Kingsville | Candidate:Ravishankar, Ravikishan Erri | Full Text:PDF |
GTID:2468390014955031 | Subject:Electrical engineering |
Abstract/Summary: | |
Integer addition is one of the most important operations in digital computer systems because the performance of the processor is significantly influenced by the speed of their adders. This thesis intends to implement a delay insensitive carry-look ahead adder using dual rail logic and to compare its performance with that of a ordinary carry-look ahead adder. |
Keywords/Search Tags: | Dual rail logic, Performance, Carry-look ahead adder |
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