The Asynchronous Router Design Of Two-dimensional On-chip Network

As system-on-chip(SoC)designs enter the billion-transistor era,more and more semiconductor IP cores are integrated into a single chip.The traditional bus-based synchronous communication architecture has limitations in terms of bandwidth,clock synchronization,and communication efficiency.To this end,the researchers proposed another system architecture-Network-on-Chip(NoC),to transplant macroscopic computer network communication methods to a single chip to achieve multi-processing systems.With the expansion of NoC communication scale,the network layout and connection are too complicated,resulting in excessive communication delay of the entire NoC system.Therefore,how to reduce the NoC transmission delay and increase the NoC throughput rate has become the research focus.Asynchronous circuit has the characteristics of delay insensitivity,strong robustness and low complexity of system integration,which is a feasible solution to these problems.According to the advantages of asynchronous circuit,such as fast transmission speed,easy modularization and flexible design,the paper proposes a new asynchronous router design scheme based on the communication between routers in NoC and the internal logic structure of the router.Under the constraints of throughput,transmission delay,power consumption and many other factors affecting NoC performance,the switch fabric is used as the basic structure of asynchronous router design.The pipeline asynchronous style pipeline,namely MOUSETRAP module,is used as the communication handshake module between routers.The two-phase handshake protocol is used as the communication protocol between routers and each module in the router.The asynchronous unit of two-phase and four-phase communication protocol conversion is designed to realize the two-phase and four-phase protocol conversion in the router.n the case of uniform and non-uniform traffic,the Most Critical Queue First-Round Robin(MCQF_RR)is applied to the NoC internal router data transmission.In addition,combined with the asynchronous router designed in this paper,the corresponding asynchronous resource network interface and network resource interface are designed.In the resource network interface,the packetizer is packaged in a parity format,and the cache module adopts the idea of time division multiplexing to reduce the latency of the read and write processes.In the network resource interface,the cache module uses the wormhole exchange mode to classify the microchips of different data packets and store them in different virtual channels,so as to ensure that each virtual channel stores the same data packet microchip;The packet reassembler adopts a double pointer write and a single pointer read method to reduce the delay of the microchip group package process;The depacketizer performs pipeline data analysis on the reassembled data packet and sends the parsed data to the corresponding resource network node.Finally,the Verilog Hdl language is used to complete the design of each module in the router,and the simulation is performed on the FPGA platform.The experimental results show that the designed asynchronous router has a single packet delay of 9.5 clock cycles and a throughput rate of 0.2Flits/Cycle/Node,which satisfies the low latency requirement for large data volume transmission.