Design And Realization Of BCH Codec Over Composite Fields

The development of disk is very slowly which became a bottleneck in the current computer system due to its literacy rate of read and write , the rapid development of semiconductor memory makes its application in the storage industry will become increasingly widespread and may even replace the disk. The high-speed semiconductor memory interface and the feature of nand flash that nand flash prone to make errors frequently caused by bit flip make the hardware codec of error-correcting codes become increasingly practical and implementation. Due to its special structure of the algorithm, linear feedback shift registers can be good used in hardware design for BCH code which makes it performs a high operation speed and small consumption of resources.The BCH coding and decoding theory is researched and a parallel algorithm of byte as the basic unit of encoding input and decoding input are developed in this study. 32-bit parallel algorithm is used in the module of chien's search algorithm of the decoder. Operators based on composite field instead of polynomial expansion is used in the encoder and decoder which performs a high efficiency and low area consumption. And ultimately implement the entire algorithm using verilog. The using of parallel pipeline structure in the overall structure makes the decoder can decode two yards words simultaneously which improve the efficiency of the decoder greatly. The design used a design idea of multiplier reuse, which makes the module for calculating the error location equation uses only 10 multipliers. Although the speed of calculate in this idea is reduced to a certain extent, but the saving of hardware resource consumption that it brings is very obvious.A comprehensive coverage of simulation platform which can automatically validate the function of the whole encoder and decoder is designed in this design. The mass simulation running on this platform ensures the correctness of the code.