Design Of 2.4GHZ CMOS RF Wireless Tranceiver

As the regine of wireless comunicaion application becomes larger, demand for low-cost low-power-consumption RF IC has been increasing drastically day by day. Therefore the idea of using CMOS technology to implement RF IC has been paid much more attention on. With great improvement of characteristic frequency of CMOS devices, CMOS RF transceiver has gradually replaced conventional bipolar or GaAs transceiver in many wireless communication areas. However, due to the intrinsic shortage of CMOS technology such as substrate loss, CMOS RF transceiver will remain a hot research topic in a predictabally long period.In this dissertation, several common architectures of RF transceiver, including superheterodyne transceiver, zero-IF transceiver and low-IF resceiver, are introduced. The characteristics of each archetecture are described and their pros and cons are analyzed. In addition, the difference in configuration between full-duplex and half-duplex transceiver is also introduced. According to the design requirements as well as the feasibility in CMOS technology, half-duplex transceiver is employed eventually. The part of transmitter is based on superheterodyne archetectur and the one of receiver is based on low-IF architecture.Upon research on fundermental theory of RF IC, these main subcircuits in RF front-end have been designed, including LNA, PA, T/R switch, mixer and frequency synthesizer.All the designs in this thesis is based on TSMC RF 0.18μm CMOS technology. Cadence SpectreRF and Agilent ADS are used to perform schematic design and simulation. Simulation results have manifested: LNA has 1.8dB NF, 15.9dB gain, 9.8mW power consumption; PA has variable output power from 0 to 9.2dBm, 33% drain efficiency, 32% PAE, 7.1 OIP3; T/R switch has -860dBm insertion loss; mixer has variable conversion gain from 13.2 to 19.5dB, tunable IIP3 from -12.4 to -7.0 dBm, 13dB DSB NF, only 900uW power consumption; frequency synthesizer has variable output frequency from 2.3616GHz to 2.5128GHz, 2.4MHz every step, 63 separate channels, 123KHz loop bandwidth, 55μs lock time. All these performances can meet the initial specification, so the original objectives are accomplished.