Research Of Frequency Synthesizer For OFDM UWB System

Driven by increasing demand of short-range and high-data-rate wireless communications, ultra-wideband (UWB) technology with high data rates and low power becomes more and more attractive and is regarded as a new poineer technology in future. In this dissertation, the design methodology of frequency synthesizers for UWB systems of WiMedia standard and Chinese standard are presented.According to the special request of frequency hopping time to be less than 9.47ns, traditional phase-locked loop (PLL) does not work. In this dissertation, two new architectures are proposed.In the research of frequency synthesizer for 3-5GHz application, the output frequency is suggested to be chosen from three parallized PLLs. For the wide frequency tuning range and low phase noise specification, this dissertation proposed a new multi-path ring-oscillator based dual-loop PLL. It combines a coarse-tuning loop with a large VCO gain for wide tuning range and a fine-tuning loop with a low VCO gain for low phase noise. A novel dual-controlled ring oscillator is designed for the dual-loop PLL. Implemented in 0.18-μm CMOS process, it shows a much wider tuning range and a comparable phase noise to previous works.In the research of frequency synthesizer for Chinese standard, SSB-mixer-based frequency synthesizer is used to generate 14 bands. As frequency spur becomes the most difficult point, careful frequency plan is made to minimize the number of SSB mixers. This dissertation proposes new frequency plan and synthesizer architecture for the Chinese standard. The system simulation results confirm that it simplifies the design and improves the output spectrum quality.In the circuit design for the frequency synthesizer, this dissertation made optimized designs for a good output spur performance. A distortion-cancellated IQ calibration module is designed to calibrate the input I/Q mismatch and suppress the non-linearity from itself. Besides that, a multi-phase/frequency selector is designed. It uses cross-coupled cancellation scheme to suppress the port leakage. Phase selection is integrated without additional power. The synthesizer is implemented in 0.13-μm CMOS process. The power consumption is 87mW at 1.2V power supply. The phase noise is-88dBc/Hz@125kHz,-105dBc/Hz@1MHz, and the integrated phase noise is 2 degree. The image spur is as low as-45dBc with IQ calibration. The performance of the synthesizer is comparable to the prior works in the world.