Research On Embedded Memory On-Line Fault Tolerant Technology

With the rapidly growing design and manufacture technology of integrated circuit (IC), the embedded memories have occupied a large amount of area in the chips. Owing to the high complexity and high frequency, it is much easier that the physical defects occur on the embedded memories and the varieties of faults is becoming larger. Thus results in the increase of testing difficulty. Because of the radiation effect from cold grains, some contents of memories cells may reverse. Especially in the conditions that the system could not stop for testing, the yield and reliability is facing unprecedented challenging, and become the choke point of SoC industry. The on-line fault tolerance technology becomes a principal means to solve the chips testing problem, which is paid attention to gradually by people. To begin with, the thesis researches the functional model and fault models of different verities and then introduces some testing and repairing technologies briefly. The paper focus on the embedded memories on-line fault tolerant technology and aims at detecting quick and efficient solutions.In the passage we firstly analysis the on-line fault tolerance method based on single bit faults. But hardware redundant brought by the method is no longer sufferable as the memory size increasing dramatically. Thus a modified scheme t is proposed by dividing the memory on-line testing into two steps: checking with parity code and correcting with the hamming code. Experiments shows, the hardware redundancy is decreased evidently.Then the transparent BIST schemes are discussed secondly. The non-concurrent method with bigger hardware redundant and lower fault coverage is not widely used. And an enhanced method based on the concurrent method is presented which is performed by replacing the register with a temporary memory. It can efficiently improve the performance of transparent BIST on fault coverage of coupling faults.Finally the MBISR circuit is researched which is between the two key points of memory fault tolerance technology. A faster MBISR method based on address partitioning strategy is proposed. It can decrease the repair and access time by simplifying the address comparison course. Experiments show that the proposed method can efficiently lower down the time dissipation and decrease the hardware redundant simultaneity.