Research And Realization Of The Test Algorithm For Embedded Memory

With the development of the submicron technology, embedded memories have occupied more area on SoC (system on chip). Because of the high frequency, complexity and the high density of the transistors and layout, the physical defacts occur on the embedded memories easily. So an effective algorithm and test method are significant to the yield improvement and product cost saving. The test algorithm is the kernel of the memory test. The inference of test algorithm must be tradeoff on the algorithm complexity and fault coverage. How to infer a low complexity and high fault coverage algorithm is the difficulty of algorithm reseach. Otherwise, the MBIST circuit is a additional test logic for chip, so area and power cost of the MBIST circuit must be limited properly.This thesis researches the 13 kinds fault primitive of single-cell faults and coupling faults, develops the test algorithm for each fault primitive. The new test algorithm (March 28) has been infered based on the optimization of these algorithms for 65nm technology. The new algorithm can optimize the fault coverage and test time. It can detect all link-faults, all single-cell faults, all coupling faults and data retention fault. The algorithm complexity reduces 12.5%. Based on the March 28 algorithm, MBIST circuits are generated by EDA tool. The MBIST logic are optimized in chip level connecting and implemented in 84 memories on a chip which is based on Infineon 65nm technology. The simulation of the algorithm proves that the March 28 algorithm can detect more fault modes than March C+ and March LR. The simulation of the MBIST circuits in chip level proves that the MBIST logic can test embeded memory without increasing I/O pad. The test algorithm and MBIST circuit in this thesis satisfy all requirements in actual application.