| Because the growth of traditional bus performance can’t keep up with the growthof processor performance, the reduction of growing speed of overall systemperformance caused by the traditional bus performance is more and more prominent. Atpresent, new bus adopt the point-to-point transmission to reduce the load, to raise thefrequency of transmission, to reduce the pin count and thereby to reduce the cost. SerialRapidIO (Rapid Input Output Interface) interface which designs for serial backplaneand DSP (Digital Signal Processor) has fewer interface pin count, higher reliability,wider application, easier realization, better scalability and lower port cost, and all ofthese characteristics make it become the representatives of the new bus and the hot topicof the research.The highest transmission rate of RapidIO specification version1.3can reach to3.125Gbps. Compared with traditional bus performance, it has been greatly improved.However in many cases it still can’t meet the chip’s requirements for higher rateinterconnect interface. In order to further improve the transmission rate, this thesisdesigns and realizes the RapidIO based on PCIE (PCI Express) physical layer IP corethat meets the requirements of2.1version of the specification, the highest transmissionrate of the new RapidIO can reach to5.0Gbps. The main research work as follows:1. Detailedly studied the composition and functions of RapidIO logical layer andtransport layer, serial protocol layer, PCS layer and PMA layer. Analyzed thecomposition of the serial RapidIO packet, the transmission and control process ofpacket on the link.2. studied how to utilize GRIO (Generic RapidIO) and physical layer IP core toform a complete RapidIO. Studied GRIO principle, carefully and respectively analyzedinbound and outbound module in GRIO. Designed and implemented the key modules ofthe physical layer.3. Studied how to have a PCIE physical layer IP core of higher rate integrated intoa GRIO chip. Carefully analyzed the composition and principle of the physical layer IPcore, separate physical layer IP core into transmission module, receiver module andclock module, elaborated the composition of each module and signal respectively andcompared to the similarities and differences between the physical layer IP core of SRIOand PCIE.4. Integrated PCIE physical layer IP core into the RapidIO, careful analyzed anddescried the configuration of the control signal. Carried a module-level verification onthe designed serial RapidIO,the result of verification and analysis show that this serialRapidIO interface has achieved the specification defined I/O logic operation, hascompleted the transmission function of the serial RapidIO (single-channel/four-channel) and has meet the design requirements of function and timing of the high-speedtransmission. |
