Digital System Design Of Serial RapidIO Physical Layer

Due to the rapid development of communications and network technology, updating the embedded processing technology is high-profiled, and it also promoted the development of the embedded system interconnection technical innovation. In order to cope with such challenges and meet the needs of embedded system development, the industry’s leading semiconductor and system manufacturers Motorola and Mercurywork together to set up a high-speed Internet Protocol, RapidIO. The RapidIO interconnect architecture, the one and only international standard of embedded system interconnection, eliminates the bottleneck by defining a high-performance, point-to-point, and packet-switched interconnect technology. And the physical layer IP is the critical part of RapidIO design.Serial RapidIO protocol consists of logical layer, transport layer and physical layer. This thesis first introduces the structure of RapidIO and the characteristic of each layer, and then divides the physical layer into Buffer sublayer, serial protocol sublayer(SPS), physical coding sublayer(PCS), and physical media sublayer(PMA). The former three sublayers are the digital control system of physical layer, and this thesis describes the working principle and realizing method of the critical modules in each digital sublayer. This design is RTL coded utilizing Verilog HDL, and thorough BIST system is embedded in order to providing test uses. On the basis of realizing the structure of RapidIO physical layer, this thesis has optimized the structure of Buffer sublayer so that better space utilization and higher transmission efficiency are achieved.Under VCS simulation environment, function simulation, loopbackmode test and system level verification are conducted. Simulation result and FPGA verification result show that, the transmit lane, the receive lane, error management, status management and link level flow control of the physical layer design in this thesis are working correctly. This serial RapidIO physical layer is taped out using HUALI 40nm CMOS technology. And the chip test result shows that, the function and performance of the designed physical layer can meet the requirements of the protocol, and the serial data rate can reach 5Gpbs.