Design Of The Data Receiver For High-speed Serial RapidIO Interface

As system-level interconnect, RapidIO is mainly designed for the communications of high-performance digital signal processing systems or embedded systems interconnect. It adopts the standard method of data transferring based on switching rather than bus interconnects, and can implement that the effective data transfer rate of 10Gbps, on four pairs of differential lines with high-performance interface. There is higher transmission efficiency than 10-Gigabit Ethernet and PCI Express. RapidIO is perfect in routing, switching, fault-tolerant and error correction. It can realize the reliable data transfer based on hardware.This paper studied the basic requirements of interface design of Serial RapidIO Physical Layer specification; Then, analyzed the behavioral characteristics of transmission line and various non-ideal factors that impact the signal integrity, based on high-speed signal transmission theory; Finally, designed the circuits and layout of data receiver in the high-speed serial RapidIO transmit system. It included programmable equalizer, sense amplifier sample circuit, differential signals to single-ended circuit and serial to parallel module.Equalizer is the core of this design. Because the high frequency components of signals is attenuated seriously, after passed the transmission line. This will make the rise and fall time of signals longer at receiver, resulting in inter-symbol interference and high bit error rate. Equalizer can compensate the high-frequency components of the signal received by receiver, through increasing the proportion of high-frequency components of the signal to restore the signal quality. So its performance decides whether the entire receiver is able to correctly identify the signal. In the entire structure, we choose multiphase data extraction technology to sample data. By using four-phase clock (from CDR) to sample the serial data, we can sample a high-speed serial data stream at a lower clock speed. The sense amplifier sample circuit is also designed carefully, especially the size of the transistor circuit need to be optimized and adjusted continuously. We should also pay more attention to match the device and reduce process errors in layout. The circuit of differential signals to single-ended is imple- -mented by SR flip-flop structure, which is composed of the cross-coupled NAND gate. Shift registers are used to realize the serial to parallel circuit. Serial data is shifted into the serial D flip-flops under the control of the bit clock, and then the data can be obtained synchronously in the parallel output registers, under the control of the word clock derived from 1/5 frequency divider. The conversion of serial to parallel is completed.