The Design Of A 10MHz-1.2GHz Wideband Programmable Pll In 65nm CMOS

In 1932, Bellectze put forward the theory of synchronous detection, and first public the discussion of Phase-Locked Loop(PLL). With the development of integrated circuit technology, especially the emergence of CMOS semiconductor technology, the phase-lock technique has been applied widely in more fields. The precise point frequency PLL with wide input and wide output range has been gradually becoming one of the hot researches field.It is well known that, PLL is a narrowband closed-loop feedback system. This paper, based on the theory foundation of PLL, a wideband programmable PLL is implemented in standard 65nm CMOS technology, the PLL with the input frequency between 10MHz to 200MHz and the output frequency between 10MHz to 1.2GHz. The post layout Hspice simulation indicates the PLL work correctly and with excellent performance, meanwhile the PLL can meet the predetermined design requirements. The research and innovations of this paper are basically as following:1. Study the related theory of charge-pump PLL, and investigate the PLL model, mathematical deduction, which lays the foundation of the broad technology for future research of PLL.2. To meet the requirement of wideband of PLL, this paper designed a wideband PLL structure which is composed of several narrowband PLL, with the input frequency range between 10MHz to 200MHz, and the output frequency range between 10MHz to 1.2GHz.3. To eliminate the performance affect from the jitter of VC, a circuit is designed that can decrease the jitter to 70% normal value for the single-ended VCO.4. Research the art of mixed-signal layout, and device matching and guide ring are used to reduce the effect of all kinks of noise, improving the performance of PLL.5. The PLL is implemented in standard 65nm CMOS technology. The area of the PLL is 0.182mm~2, and the power dissipation is less than 10mW at the worst case, the frequency range of VCO is between 0.9GHz to 2.5GHz, the input frequency range is between 10MHz to 200MHz, and the output frequency range is between 10MHz to 1.2GHz. The pre-divider, feedback-divider and post-divider can achieve a frequency divide of 1-32. The RMS jitter and peak-to-peak value jitter are 250.129ps and 32.125ps respectively at the worst for input frequency of 50MHz and output frequency of 200MHz.6. The PLL was tapouted and PLL samples have been tested. The test result of sample indicates that the performance of the PLL sample is accordance with the simulated result, meeting the the design requrements.