Signal Integrity Simulation And Testing For Large - Screen Splicing Technology

Considering the cost and the video quality, the display device was oftenchosen with small size. So in the monitoring room there was a large screenin the middle position of Video Wall and several small ones on both sidesusually. With the reduction of the screen manufacturing cost and thedevelopment of high-definition image technology, more and more customerstend to choose the large screen in their monitoring room instead of the smallone. Thus we could have much more clear images with low wiringcomplexity in monitoring room. Correspondingly, we wouldn’t havemultichannel video at the same time. So the method of image displaying onlarge screen through computer encoding appears. And it solves the problemof multichannel video displaying on one big screen in real-time which losingpart of video signal quality. Based on the requirement of multichannel videodisplay on single screen without image quality reduction, this thesisprovided a kind of method to solve the requirement after comparing severalmain seamless mosaic technologies on large screen nowadays. The method supported the flowing functions: four channel SDI/DVI-I/CBVS inputs(thehighest definition is1920x1080@60p),one channel DVI-I/SDI video outputwith adjustable definition on DVI-I video output. The method also coulddisplay four channel real-time video on a single screen at the same time, andthe video is free of roaming and zooming.The main idea of this method is using FPGA to convert the four channelinput video into one channel output video without reducing video qualityand delay.In order to fulfill the interface requirement of frame rate alterationand resolution conversion, we should supply enough memory space to FPGAfor completing the related arithmetic operation. We evaluated the memoryspace for the largest scale data calculation. After analyzed the high-speedmodels of passive component such as resistor、capacitor and via, wesimulated the topology style and driving capacity of signal between FPGAand DDR2. Thus we solved the signal quality problem. We also solve signaltiming sequence problem after simulating the timing sequence. And theprogram developed by using matlab could measure signal timing sequenceparameters automatically, which produces a fast and convenient way toverify simulation result accurately. For overcoming the problem of powerripple and noise, we adopted the target impedance method to analyze thedecoupling capacitor type and quantity of the capacitor. In the last part of this paper, we introduce both the measurement method of signal integrityand measurement device, and take the signal integrity measurement by usingoscillograph. The measurement results show the PCB design whichaccording to the simulation requirements is meeting the requirements ofsignal integrity.