| As a basic function unit of digital signal processing, finite impulse response (FIR) digital filters have advantages of stability, linear-phase, arbitrary amplitude, design flexibility. It has been widely used in many fields such as communication, radar, image processing and speech processing.Traditionally,the hardware used for real time implementation of FIR filter mainly include MCU,DSP and ASIC,etc. In practical applications, the characteristics of real-time,high-speed and flexibility are required for signal processing. However, most of the traditional hardware and software techniques which are available for the implementation of FIR filter are difficult to satisfy all of these requirements at the same time. With the development of PLD device and EDA technologies, FPGA has the characteristics of flexible programmable logic which can be conveniently used for implementing real-time digital signal processing, because it break through the level limit of parallel processing and pipeline technology. The resource of FPGA can be utilized effectively because it has the characteristic of reconfigurable logic resource on chip. More and more researchers who engage in digital signal processing are favoring FPGA.The paper mainly do study on the implementation of FIR filter targeted FPGA with the purpose of reducing system resource consumption,improving system processing speed and improving resource utilization rate. We mainly start the work on the development method and algorithm structure to reach the aims. The main works carried out in this paper are as follows:1) The methods of designing FIR filter which are based on SYSGEN and DA are introduced in this paper. Appropriate method of implementing FIR filter targeted FPGA is studied on the basic of the thoery of FIR filter design and FPGA implementation.2) In order to solve the promblems of too much resource consumption,too low processing speed and too low resource utilization rate using the traditional SYSGEN method, a cost-efficient method of designing FIR filter targeted FPGA is proposed. First of all, the proposed AS FIR filter architecture is adopted to reduce resource-consumption, increase speed processing and improve resource utilization rates of the system, and then SYSGEN and ISE are used together to implement FIR filter targeted FPGA modularly and automatically. A series of FIR filters which order from 4 to 32 are implemented targeted XC3S500E4f320 FPGA. Design examples show that our method is very efficient.3) Concerning the problems of too much resource consumption and too low processing speed using the traditionnal distributed arithmetic, a new method of implementing high order FIR filters targeted FPGA is proposed. Firstly, polyphase decomposition architecture and pipeline technology are adopted to decompose high-order FIR filter into low-order ones, and then the proposed MA distributed arithmetic architecture is used to implement the subfilters in the method. A series of serial and parallel FIR filters which order from 8 to 256 are implemented by ISE10.1 targeted Xilinx Xc2vp30-7ff896 FPGA device. Design examples show that our method can implement FIR filters with smaller resource usage and higher speed.4) A FIR digital filter system based on FPGA is designed, and the main modules of the circuit system and its function are analyzed in the paper. The system proposed in this paper have the characteristics of convenient program download,easy expansion,strong universality and real-time and so on.The methods proposed in this paper for the design and implementation of FIR digital filter on FPGA are of certain significance in both theory and engineering. Our work can not only improve the performance of FIR filter system but also reduce its designning costs. |
