| In the modern electrical systems, the finite impulse response (FIR) digital filter, as a basic module of digital signal processing, is employed in many practical applications due to its good characteristic of linear phase and small phase distortion. In engineering practice, signal processing is often required to have the properties of real-time and flexibility. However, FIR digital filter’s implementation only by software or hardware technique is difficult to satisfy the both demands. Along with the development of Programmable Logic Devices (PLD) and Electronic Design Automation (EDA) technology, the implementation of FIR filters based on Field Programmable Gate Array (FPGA) becomes an issue of research interest, as it not only meets the real-time requirement, but also has some flexibility.In this paper, followed with the classification of the digital filters, the basic theory of digital filters was first introduced. The features of different filters were analyzed, and the basic characteristics and the structure of the FIR digital filter was specially illustrated, by which the scheme that in this research FIR with the linear phase would be employed to minimize the hardware resources occupation was determined.Secondly, several methods to design FIR filters were illustrated. The design of filter is in fact the approximation of the ideal frequency response in different ways. According to the different approximation ways, the design methods can be classified into window method, frequency sampling method, and equal ripple approximation method. Based on the principle of each method, the basic steps of the design were proposed and difficulty in the design was addressed, providing the theoretical support of the subsequent design. By the analysis and discussion, the scheme that the window method would be employed to design the low pass filter was confirmed.Thirdly, the methods of implementing FIR filter using FPGA were firstly introduced and the distributed arithmetic algorithm was employed as the scheme of hardware implementation for the filter. To scale down Look-up-Table (LUT) in the distributed arithmetic algorithm and improve the performance of the filter, the LUT was separated based on the symmetry of linear FIR filter.Based on the above discussion, an18order low-pass filter was successfully designed in Chapter5. By using a hierarchical, modular idea in the design, the whole system was divided into several smaller functional modules, which was designed with Hardware Description Language (HDL). Each of the functional modules was synthesized and simulated with Quartus II. And also the result of the simulation was analyzed with the use of MATLAB, and it indicated that the goal of the design has been achieved. |
