The Design Of FIR Filter Based-on Distributed Arithmetic And Implementation By Using FPGA

With the wide applications of modern electronic system, the users pursuit the fulfillment of real-time,hign-speed and reliable digital signal process.The FIR digital filter is critical to real-time signal processing due to it strictly linear phase character. The improvement of speed and integration of PLD makes a new approach to achieve real-time,high-speed and reliable digital signal processing with hardware is avilable. FPGA is one of the most usually used PLD,and its architecture of LUT is applicable to implement FIR filter.HDL hardware description language's flexbility and independence with hardware makes the implement of FIR filter based on FPGA by using HDL a new research field.In this paper, the implement of FIR filter using FPGA based on Distributed Arithmetic (DA) is studyed.The basic principle,the design flow,the commonly used design method and technical of FPGA are introduced;the basic theory of FIR filter and several commonly used window functions are discussed;the parallel, serial, integrate of parallel and serial implementation of DA are studyed, especialy put emphasis on the implementation of pipeline of parallel.In the process of design FIR,use repeatly configurable LUT and HDL to operate DA to shorten the tradition design of MAC; adopt table separation to separate LUT to reduce the scale of LUT; the independence of LUT parameters from filter's structure can provide generally useness and be more easy to modularizate the filter to favor the maintenance and expandence of the system;make simulation of filter modules and compare the result with MATLAB direct operation result to testify the accurate of the design.The result of the simulation indicated that the scale of the design is small,the digital filter has the characteristic of real-time,high-speed and reliable.