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Implementation Of Digital Filter With Optimal Distributed Arithmetic Based On FPGA

Posted on:2017-02-22Degree:MasterType:Thesis
Country:ChinaCandidate:X X ZhuFull Text:PDF
GTID:2308330485991302Subject:Control Science and Engineering
Abstract/Summary:PDF Full Text Request
The FIR filter has strict linear phase frequency characteristics relative to IIR filter. The feature makes the FIR filter has a wide range of applications in data transmission, image processing and recognition, speech processing and communication system. To achieve linear phase the IIR filter need to post a all pass filter with increasing the complexity of the whole system. In addition, the FIR filter has no other poles except 0, so the whole filtering system is relatively stable, and there is no problem of instability. The above two points are the value of the research of FIR filter in this paper.Due to the advantages of FPGA in cost, power consumption, flexibility, performance, stability, processing speed and so on. The design of electronic circuits with FPGA is the trend of design. Based on the advantages of FPGA relative to other micro controllers, this thesis selects FPGA as a controller to design a Linear phase high order FIR low pass filter.The filter based on DA algorithm can effective solve the problem of MAC structure, but as the filter order number increase, the scale of the look up table increases exponentially. If we want to design a 32 order linear phase structure of the FIR low pass filter, since the linear phase of the filter coefficients is symmetric, we need the address of the table is 216that is equal to 65536. From this, we can find that the scale of the look-up Table is quite large, and it is difficult to realize in reality. This paper proposes an optimized DA algorithm to overcome this defect, and it is implemented on FPGA.In order to verify the correctness of the proposed optimization algorithm, the index of the filter designed by this paper is that:Sampling frequency fs is 48000Hz; cut off frequency fc is 8000Hz; minimum stop Band attenuation A, is-30db; with the band less than 1db; the order of the Filter is 32. Using verilog HDL on the FPGA to complete the algorithm, and simulation on Modelsim tool.Through the simulation results of Modelsim and the theoretical value of MATLAB calculation, we can know that the system design can be correctly and steadily running. The correctness of the optimization algorithm and realization of the algorithm are also verified. It can be applied to a low pass filtering system that maintain a strict linear phase, it is proved that the higher the filter order, the more obvious the effect of the optimization algorithm, and also can save the internal logic resources. This design meets the expected results.
Keywords/Search Tags:high order filter, linear phase, FPGA, optimization of DA algorithm, 32 order
PDF Full Text Request
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