High-end Fpga-based Fir Filter Design

With the development of the technology, the design of the electronic circuit is getting rid of traditional pattern, while using FPGA to design electronic circuits is becoming the trend of design. Because using FPGA to design electronic circuit have the advantage of short time and relative less fund, and can make product as electronic circuit to product as chip.In the modern electrical system, the FIR digital filter is used for many practical applications for its good linear phase character. In engineering practice, there is always a real-time and flexible requirement for signal processing. However, traditional pattern are difficult to meet the demand for the two aspects in the same time. More and more people use FPGA to implement FIR filter, as it not only meet the real-time requirement, but also has some flexibility.This paper focuses on the implementation technology of digital filters based on FPGA, with the background of the implementations of digital signal processing system. It contains three main parts:1 . According to the basic theory of FIR filters, three schemes of hardware implementation are worked out using MAC, parallel multiplier and distributed arithmetic algorithm. As the scale of multiplier in the MAC algorithm is so large, the thesis reduces it with the use of canonic signed digit coding and as the scale of LUT in the distributed arithmetic algorithm is so large, the thesis reduces it with the use of multiple coefficient memory banks.2. From the clew of implementing a stratified, modular design, the thesis describes the hardware design of all functional modules and the FIR system with the Verilog HDL.3. At last, a one-hundred-twenty-eight tapped low-pass FIR filter based on Altera's Stratix is taken as an example, and the simulation design carried out using ModelSim. The result of the simulation is analyzed with the use of MATLAB.