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Research And Design Of On-Chip High Performance CMOS Power Supply Converter

Posted on:2010-08-30Degree:DoctorType:Dissertation
Country:ChinaCandidate:Q N ZhouFull Text:PDF
GTID:1118360278496106Subject:Microelectronics and Solid State Electronics
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With the development of CMOS industry technique, many circuits of function blocks are integrated into single system on chip (SoC), and the on-chip power supply converters are the important circuits of SoC. In this dissertation, aiming at the physical area, standby power and power supply rejection (PSR) of power supply converter, on-chip high-performance CMOS power supply converter are researched and designed. The main researches in this dissertation are:Firstly, on-chip power supply converter, which is based on current-boosting technique and weighted single-threshold voltage, is presented by applying the bulk effect phenomenon of MOS transistor. When the maximum load current is 100mA, comparing with the power supply converter without curret-boosting technique, the aspect ratio (W/L) of the PMOS pass element in the presented power suply converter is decreased from 4.28k to 3.96k, and its whole physical area of power supply converter will decrease. And the transisent response time of the converter is decreased by 5.26%.Secondly, two kinds of on-chip low standby-power power supply converters based on weighted different-threshold-voltage are designed and implemented by HJTC 0.18μm technology, and these converters are on-chip power supply converter based on the current source operating in moderate inversion region and on-chip power supply converter based on the current source operating in weak inversion region. Experiment results show that the converter based on the current source operating in moderate inversion region consumes the standby power of 38μW, and its output voltage achieves temperature coefficient of 0.772mV/oC, line regulation of 42mV/V and load regulation of 0.35mV/mA. And the converter based on the current source operating in weak inversion region consumes the standby power of 24.6μW, and its output voltage achieves temperature coefficient of 0.972mV/oC, line regulation of 21mV/V and load regulation of 0.284mV/mA.Thirdly, utilizing the technique of the pre-regulator and long-channel PMOS resistors, a high power suppy rejection (PSR) sub-1V bandgap reference (BGR) without resistors, which is suitable for on-chip CMOS low dopout (LDO) regulator, is presented. And the presented bandgap reference is, respectively, designed and implemented by 0.18μm and 0.6μm technology. Experiment results show that the implemented BGR by 0.18μm technology at 100Hz, 1kHz and 10kHz achieves the PSR of -70dB, -62dB and -43dB respectively, and the implemented BGR by 0.6μm technology at 100Hz, 1kHz and 10kHz achieves the PSR of -68.9dB, -61.2dB and -44.6dB respectively. Measured results show that the presented BGR, which is implemented by different kinds of technology, has comparable performance.In the fourth, an AC-boosting and active-feedback frequency compensation (ACB-AFFC) technique of three-stage amplifier is proposed in this dissertation. Based on the ACB-AFFC technique, an ACB-AFFC three-stage amplifier is designed by 0.18μm CMOS technology. Simulation results show that the ACB-AFFC three-stage amplifier achieves about 100dB dc gain, a gain bandwidth of 7.5MHz, phase margin of about 67o and slew rate of SR+/-=1.1/1.19V/μs. Then, adopting the technique of dynamic feedforward and CSMC 0.6μm CMOS technology, an ACB-AFFC three-stage amplifier with dynamic feedforward stage (ACB-AFFC-DFS) is designed and implemented and it has a simpler architecture. Measured results show that the ACB-AFFC-DFS three-stage amplifer achieves a better slew rate of SR+/-=2.4/4V/μs.Based on the ACB-AFFC-DFS amplifer and the high PSR sub-1V BGR without resistor, a capacitor-free CMOS LDO regulator is proposed and implemented by 0.6μm CMOS technology. Measured results show that the proposed CMOS LDO regulator achieves 5.42mV/V line regulation and 0.35mV/mA load regulation. On the basis of the designed LDO regulator, a system of capacitor-free CMOS LDO regulator, which include the over-temperature and over-load current protection circuits, is designed by 0.18μm CMOS technology, and the system achieves that temperature coefficient of 7.6ppm/oC, line regulation of 0.015mV/V, load regulation of 0.003mV/mA, and the PSR of -85dB and -30dB at 100Hz and 100kHz respectively.Finally, the application of CMOS LDO regulator is analyzed and discussed. On the basis of the CMOS LDO regultator designed in this dissertation, a preamplifer of optical receiver is analyzed and designed, and the operating supply voltage of transimpedance amplifer in the preamplifer is the output voltage of LDO regulator. Simulation results show that PSR of the transimpedance amplifer is improved from -7.43dB to -84.5dB by adopting LDO regulator.
Keywords/Search Tags:On-Chip Power Supply Converter, Low Dropout Regulator (LDO), Bandgap Reference (BGR), Three-Stage Amplifier, Preamplifier
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