Design Of Multimode Fractional-N Synthesizer For Single-Chip CMOS Transceiver

With the continuous development of wireless communication technology and the introduction of a variety of wireless communication protocols, fully integrated single-chip wireless transceiver become the most popular research focus. This requires frequency synthesizer (the key module to the wireless transceiver) to provide highly stable, high reusability, low phase noise local oscillator signal to meet the needs of a variety of communication protocols. So, communications IC manufacturers and IC designers in universities and other research institutes have developed a lot of multi-mode multi-band frequency synthesizer chips or IP cores. A frequency synthesizer is proposed for the UHF RFID,WCDMA,TD-SCDMA,IEEE 802.11 a/b/g in this thesis.First, structures of phase locked loop are reviewed. The basic principles, loop parameter and phase noise of delta-sigma fractional-N frequency synthesizer are analyzed.Then, several broadband frequency synthesizer implementation methods are compared.A new frequency synthesizer structure is proposed. A 3-4GHz low phase noise LC VCO and a 5-6GHz low power LC VCO combined with two CML prescalers make the frequency synthesizer conver output frequency range from 0.8GHz to 6GHz。For low phase noise VCO design, three methods are adopted. On-chip LDO is utilized to suppress noise from power supply. Symmetrical noise filtering technique is used to suppress thermal noise from tail current and parasitic resistors of bonding wires.High quality factor inductor up to 16 can lower the phase noise obviously.A third order four bits output delta-sigma modulator is implented with serveral accumulator and D flip-flops.A frequency tuning range from 0.7GHz to 5.55GHz delta-sigma fractional-N synthesizer is implemented with 0.13μm 1P8M RFCMOS. The die size is 2.2mm×2.2mm. Measurement results indicate:total power is 250mW;the minimum frequency is 700MHz, with phase noise-128dBc/Hz@1MHz; the maxium frequency is 5.55GHz with phase noise-124dBc/Hz@3MHz;phase noise merits can meet UHF RFID,WCDMA,TD-SCDMA,IEEE 802.11 a/b/g communicaiton specifications.This thesis's work is supported by project "Key IP cores design for the embedded multi-mode multi-band transceiver" under the state key item of "core electronic devices, high-end general chips and basic software product" (Project number: 2009ZX01034-002-002-001-02).