A Fpga Embedded Block Ram Design

With the field-programmable gate array (FPGA) rapid growth of the number of gates, embedded memory has become an integral part of the internal circuit, embedded memory must meet several features:■flexibility, data bit width and depth can be self-configuration;■compatibility with the FPGA circuitry to meet the FPGA routing design principles;■synchronous design, this is the inevitable demand for large-scale FPGA circuit;■design for testability, DFT can be used or built-in self test BIST.In this paper the design for FPGA and memory combines ideal, it's different from single-chip memory, it is a system application, compatible with the system, the paper highlights the following points:1. Circuit can be configured with different bit-wide Implementation;2. the memory initialization circuit for FPGA initialization;3. Single-ended memory to achieve FIFO functionality of FPGA implementation;4. Built-in self test circuit to join.The circuit can be configured to 2K×1b, 1K×2b, 512×4b,256×8b working modes. With the single-ended memory, the FIFO memory function can be realized in the FPGA architecture. To achieve the greater utilization of resources, the overall circuit can support initialization of the embedded memory writing, it can achieve large-scale lookup table, multiplier, shift register and other complex functions. It is diffcult to test Embedded memory , so we design this circuit which can support Logic Built-in self-test (Logic BIST). After the circuit is turned out, it functions correctly and the performance is perfect. It's timing characteristics can achieve the objective of circuit design.