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Embedded Computer Design For Testability

Posted on:2010-08-25Degree:MasterType:Thesis
Country:ChinaCandidate:Y M BaiFull Text:PDF
GTID:2208360275991575Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
The Fault diagnosis based on Boundary-Scan has transcended the traditional detect theory,and can resolve VLSI(Very-large-scale integration) testability problem that other technology cannot.It can also resolve the board-level test and system-level test of digital devices that includes programmable VLSI devices(CPLD & FPGA), microprocessors and digital signal processors.The boundary scan technology has been most widely applied in the field of testability design and it has introduced a series of international standards.As the first protocol of boundary-scan technology, the aim of IEEE 1149.1 is to perform board-level interconnecting test,chip test and the circuits' dynamic observation and modification.The research of this paper is funded by the project of DFT(Design for testability) and test platform for embedded computer system.This paper first discusses the developments of present test technology and adds the address ability to 1149.1,which uses hierarchical structure to support system-level test.Then the main idea of Boundary-Scan technology and its system-level implementation is explained in details.The main contents are as follows:1.Introduces the DFT technology and summarizes its main advantages and implementation.2.Particularly discusses the main thoughts of Boundary-Scan test technology that is the most popular DFT technology,describes the basic structure of Boundary-Scan cell.3.Introduces the characteristics of SJTAG and the structures of its software and hardware.4.By focusing on the development of SJTAG-supporting boundary-scan test system, the paper first introduces its hardware implementation,and then explains the whole software framework.The test software modules consist of:PCB files parsing module, test vector generation module,test vector loading and chip status control module,fault type and location addressing module,graphical user interface module.This software system can perform tests on embedded computer with a Boundary-Scan chain,and it supports international standard test vectors - Serial Vector Format(svf),proving itself universal.
Keywords/Search Tags:SJTAG, IEEE1149.1, JTAG, DFT, Testability, Boundary-Scan, Test system, Fault diagnosis, Interconnect test
PDF Full Text Request
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