| More and more mixed-signal devices are being designed recently for the applications of multimedia, wireless communication, and portable data systems. The analog circuit technology conventionally employed for such applications has been gradually switched to analog/digital mixed-signal circuit technology. Even though much more complicated digital circuits have been widely used in the DSP-based mixed-signal IC, analog circuits will remain for processing or interfacing analog signals. Integrating both digital and analog on a single chip has improved performance and reduced board size and cost. However, the increasing complexity of mixed-signal circuits drastically reduces the controllability and observability of the circuit on the chip. As a result, testing of such complex circuit becomes very difficult and expensive. Therefore, the goal of the thesis study is to develop an efficient testability design system for analog/mixed-signal circuits so that all designed circuits are easily testable.;Based on the hierarchical fault macromodeling process, a hierarchical testability design system, namely, PETOMIC (Packages for Enhancing Testability Of Mixed-signal Integrated Circuit) is also developed. The system generates cell library, macro library, test set, and evaluates the fault coverage. The system has been developed and implemented in C language, Spice, and Matlab. The detail system development is discussed with examples of generating a cell library of an Opamp and a macro library of a current copier.;Some testability enhancement methodologies have also been developed in this study. Based on the given design specifications, a set of discrete inputs used for design verification, and the fault types, a set of testability design rules is developed to ensure the existence of the circuit parameter deviation bounds for these discrete inputs and for all fault types. These parameter deviation bounds are used to generate test vectors. Thus, the designed circuit can be easily testable. In addition, a high-accuracy current comparator is developed as a built-in tester (BITER). The use of BITER not only enhances the testability, but also simplifies the test generation process and reduces the test sequence length.;The thesis study has developed efficient testability design methodologies and testability enhancement methodologies. The developed design methodology defines a set of fault types from circuit layout, technology data, and process defect distribution, and it generates a set of test vectors based on the parameter deviation bounds which are derived from the design specification, discrete input set, and defined fault types. The test vectors and parameter deviation bounds allow us to evaluate the fault coverage of a designed analog circuit. This methodology was developed using the inductive fault analysis (IFA) technique. However, the IFA technique requires a tremendous amount of computational time and thus it has been limited for small circuits. For reasonable large analog circuits, a hierarchical testability design methodology is developed to reduce the computational complexity. Basically, a designed circuit is decomposed into many components. The components can be further decomposed until they can be handled comfortably by the IFA technique. In other words, a circuit is decomposed as primitive cells and/or macros. |
