A FPGA Implementation Of A 10Gb/s Ethernet MAC Controller For Lossless Ethernet

Nowadays, in the era of Cloud Computing andBig Data, the research about converged network is developing very fast, and Fiber channel over Ethernet(FCoE)which is aimed to accelerate the converge of Fibre Channel Storage Area Network and Ethernet is currently a research focus. FCoE basedconverged network has less energy consumption,less complexity of topology, less cost of equipment and manpower, buthigher efficiencyof utilization. Thus, it will accelerate the development of big data and cloud computing industry.The realization of FCoE converged network needs the support of lossless data transmission in the layer of data link, but for now the traditional Ethernet protocol which is used in data link layer cannot meet the requirement of frame transmission in FCoE network. Frame transmission in converged network must have the support of lossless Ethernet, which is also called data center bridge(DCB). And different traffic classes have multiple transmission requests, but the traditional Ethernet protocol in the layer of data link are not satisfied, Multiple traffic classes transmission of converged network, variety of flows sending schedule and frame lossless transmission can be only achieved by DCB.Upon this circumstance, based on the relevant communication protocols of FCoE network data link layer such as FCoE protocol mapping, IEEE 802.3ae-2002, IEEE 802.1Qbb and IEEE 802.1Qaz, this article designed four modules of 10Gb/s Ethernet MAC for DCB according to the desire of FCoE converged network adapter chip, i.e., multiple traffic class transmission datapath with ETS function, multiple traffic class receiving datapath, PFC flow control module as well as themanagement and configuration module. These four modules are integrated to form a10Gb/s Ethernet MAC controller for DCB. This controller interface includes AXI4-Stream high-speed data interface, AXI4-Lite control bus interface, XGMII interface and MDIO interface. In this thesis,a Virtex-6 FPGA ML605 evaluation kit, the xc6vlx240 t FPGA chip and the ISE design suitefrom Xilinx coorporation were adopted to do the RTL level circuit design, synthesis and simulation of the four modules and 10Gb/s MAC controller. Through analysisof the simulation waves and the synthesis report, it is proved that the functional correctness of data transmission and receiving, PFC function, ETS function and management function are realized. Furthermore, it is presented that the speed of data transmission can be up to 10Gb/s theoretically.