Design Of 10M/100M Ethernet Controller Based On FPGA

With the continuous development of Ethernet, the speed of transmission is evolving from 10M/s to 10,000M/s. Using FPGA to realize the Ethernet controller connecting with other SOC systems is becoming hot research at present. This paper discussed the design of MAC layer's function base on FPGA, the simulation of the MAC layer, introduce the internal structure of the whole system, module partition, and described the design of each module detaily, describe the development environment, simulation tool, method of experimental in detail, then gave the test scheme, verification data, timing stimulation wave and so on .According to the main function of MAC layer, such as transmission module, receiving module, MAC flow controlling module, reg module, MII interface module, host interface module, crc, CSMA/CD algorithms and so on, the paper gave the solutions based on FPGA and VerilogHDL.This topic aiming at three fields to research obtained a certain achievements:Firstly, the task had builded the development platform of FPGA hardware. It adapted the XC3S1000-ft256-4-C of Xilinx and ATMEL AT91RM9200 as kernel device. Using Intel LXT971 as phy chip, adapted AT91RM9200 as source data, block ram as frame buffer builded the platform.Secondly, the task had realized the Ethernet controller based on FPGA. Using VerilogHDL language implemented the design, realized CSMA/CD protocol, 10M/100M adaptation, PHY MII interface and so on.Thirdly, it had adapted general Wishbone interface on chip. Aiming at using the WS interface implement interlinkage between different design. It also provided condition for building SOC processor.The design realized the Ethernet controller ip core based on wishbone interface, accumulated experience for design Ethernet controller with self-determination knowledge property right. It also provided conditions for connecting to other controllers with wishbone interface.