Research On Architecture And Key Algorithm Of H.264 Decoder

Digital video applications have penetrated into every nook of people's lives and present a development trend of high-definition, complication and diversification, which raise higher request on the processing capability of digital video codec system, the adaptability to a complex environment and the ability to meet the diversified demand.This paper focuses on the digital video decoder, a core component of the digital video application terminal as the research object and makes an intensive study of the design and implementation of H.264 decoder according to the currently popular H.264 video codec standard on the aspects of system design, module design,error concealment and directly reducing resolution decoding. The specifics and innovations are as follow:1. To decode high definition video, the architecture of H.264 HD realtime decoder chip was analized and designed on the basis of H.264 theoretical decoding model.And the scheme has been verified. An H.264 decoder architecture with dual bus was proposed to relieve the stress of the bandwidth of system bus as well as to add as little complexity as possible. The switching buffer module SBM in data-driven asynchronous pipeline was designed to balance the different processing speed between different modules and the different speed that one module processes different macroblocks. Compared to traditional asynchronous pipeline, the one with SBM can save up to 11% on-chip memory and 31% I/O operations between stages. To simplify the management logic of decoded picture buffer, a DPB data storage orgnization was suggested.2. To meet the performance requirement of decoder module according to system design,the modules was optimized and realized based on the thorough analysis of the principle of major modules in decoder. The module can decode correctly with the FPGA verification system working frequency of 81 MHz, which verifies that each module conform with the module requirement for realtime HD decoding system. The following optimization methods are studied in module design process:bigger tables are divided into small ones which can be easily implemented with combinational circuits according to the number of leading zeros in bitstrcam and the look up table algorithm is realized with combinational circuits.Non-blocking assignment method was used to implement the butterfly algorithm of IDCT transform, which is pipelined with blocks. The intra/inter modules are divided further for pipeline process,and memory on chip was allocated to buffer the information of neighbour blocks. DPB memory controller was designed to simply the memory access logic design of module.3. To deal with the influence of transmission error to video decoding, the whole frame loss error concealment algorithm based on optical flow theory was improved. The improved algorithm is easy to realize and there is no obvious block effect and distortion in reconstructed video images. The reconstructed video quality exceeds that of existing algorithms, and can avoid the error diffusion effectively. A universal realtime error concealment algorithm was suggested based on the improved algorithm,which is suitable for hardware implementation and can used for the loss of both the whole frame and some blocks. The algorithm outperforms the H.264 JM reference algorithm in PSNR and error propagation. It can solve two problems, whole frame loss and some blocks loss, in one algorithm, which can reduce the logic resource consumed while hardware implementation and achive the goal of saving cost.4. To the situation that terminal devices with different definition co-exist in one video application, the decoding algorithm of directly reducing the spatial definition of high definition bitstream was proposed. And a novel decoding algorithm framework of directly reducing spatial definition was introduced, which will not change the framework of standard decoder and can avoid the too many changes of decoding parameters. In consideration of the new feature of H.264, a directly reducing spatial definition algorithm of residual was suggested by studying the directly reducing spatial definition algorithm of integer IDCT. Meanwhile, the intra prediction formula of the directly reducing spatial definition algorithm was introduced for intra coded macroblocks. And the method of reference block scaling was proposed for inter coded macroblocks, which can reduce error drift effectively without increasing decoding complexity. The simulation results indicates that the proposed improved algorithm can improve the decoding image quality by a wide margin in the precondition that does not increase even reduce system complexity.