The Study And Design Of A 4th-Order Sigma-Delta Modulator

ADCs fulfill an important role as the link between the analog world and the powerful digital processing environment in today's DSP systems. The rapid growth in both wired and wireless communication systems has stimulated the development of data conversion interfaces which can be integrated in standard CMOS technologies while meeting stringent resolution and linearity requirements at increasing Nyquist conversion rates. Among the wide variety of ADC architectures, Sigma-Delta ADC is an optimum candidate to meet the performance requirements of communication systems because it provides an efficient way of trading off speed for resolution.The basic theory of Sigma-Delta modulator is introduced at first. Detailed analysis has focused on the principle of noise shaping of the quantization noise. It is concluded that the modulator can achieve a high resolution with a wide bandwidth using high-order noise shaping. Next, the design aspects of the high-order cascaded modulator are studied. After a comparison of various Sigma-Delta modulator topologies, the 4th-order modulator has been implemented with a 2-1-1 cascaded structure. Then the specifications of the main analog building blocks are determined through analysis and behavioral simulation of the nonidealities of the modulator. Finally the circuit implementation of the modulator is discussed. A fully differential telescopic OTA with gain enhancement has been designed for the first integrator, followed by the careful design of the rest subcircuits. The modulator is implemented with fully differential switched capacitor circuits in 0.35μm N-well CMOS process with a 3V power supply. It achieves above 14 bits of resolution over a bandwidth of 1MHz and dissipates about 41mW. This modulator is suitable for communication applications which demand high resolution with high conversion rates.