Continuous-time Sigma Delta Modulator System-level Design And Modeling Methods

This dissertation investigates the system-level design techniques of the wide-band, power-efficient continuous-timeΣΔA/D modulators with high resolution (>12bit). Impulse Invariant Transformation is used to transform the loop filter from z-domain to s-domain. A method of optimizing the gain factors of the integrators within the loop filter is proposed based on the consideration of circuit-level design. Non-idealities of the continuous-timeΣΔmodulator are system-level modeled and simulated. Upon the low power design consideration, a hybrid active-passive loop filter is employed and the signal summing block is removed by using discrete-time differentiation technique. DWA(Data Weighted Averaging) algorithm is employed in design of the multi-bit feedback DAC to average the mismatch error and reduce the harmonic distortion.A 5th-order,3-bit continuous-timeΣΔmodulator is taken as a design example. The chip is fabricated in SMIC 0.18-μm 1P6M CMOS technology. The experimental results show that it achieves peak SNR of 80 dB, peak SNDR of 78 dB and dynamic range of 84 dB over a 1 MHz signal bandwidth when clocked at 128 MHz. It dissipates 9 mW from a 1.8 V supply. The design example has verified the design methodology.A final practice is made on further reducing the static power of the modulator. The comparators in the conventional flash ADC are replaced by the asymmetric comparators with internal referencing, resulting in the benefit of removing the resistor-ladder used to obtain quantization levels in the conventional flash ADC. This technique reduces the static power of the modulator by 20%.