Audio Low-voltage Continuous-time Sigma-delta Adc And Implementation

Basing on the National 863's Plan, this paper presents aⅠ-Ⅴ,16-bit,20-KHz bandwidth continuous-time Sigma-Delta modulator for hearing-aid applications. Compared with discrete-time sigma-delta modulatours implemented with switch-capacity technology, continuous-time sigma-delta modulators have the advantage of a lower power consumption and inherent anti-alias filtering. The presented modulator utilizes an 1-bit quantization 4th order feed-forward loop with a OSR of 128. It is implemented in active-RC integrators. A 2-stage class A/AB amplifier is designed to meet the low voltage supply requirement. A constant delay is introduced to solve the signal-dependent delay. The digital decimation filter is realized with a cascade combination of a comb filter and two half-band filter. The comb filter is implemented as a 8-4 cascade structure to realize a down sampling rate of 32. All the filter is FIR filter with utilizing sampling transposing and poly phase sampling technologies, so that the power consumption can be reduced.The modulator is realized by SMIC0.13-μm Mixed Signal CMOS process, the core chip size is about 0.64x0.36 mm2 and the power consumption is about 110μW. The chip can work underl V, clocking at 5.12 MHz with a bandwidth of 20KHz. The modulator can achieves a peek SNDR of 108 dB and a peek SFDR of 110.5 dB.