Dtmb System In The Design And Implementation Of Ldpc Decoder

Error correction coding has become an important method for communication systems to improve the transmission reliability. Because of its outstanding performance and low implentment cost, LDPC code gains increasingly interests of researchers and is employed to various communication standards. LDPC (inner code) concatenated with BCH (outer code) is adopted by Chinese Digital Terrestrial Media Broadcasting (DTMB) system. The DTMB standard’s error correcting performance approaches the Shannon’s limit. Hardware design of LDPC decoder is discussed in the thesis for satisfying the DTMB system requirements.Based on the reviewing of the LDPC code structure of the DTMB standard, the hardware design of LDPC decoder is researched in two aspects:one is the decoding algoriothm and the other is decoder architectures. The main contents are as follows:1. Study the iterative decoding algorithm for LDPC code. The belief propogation algorithm and its simplified methods are investgated in detail. The algorithm performance is analyzed and simulated. The Offset BP-based algorithm and the Normalized BP-based algorithm are compromise between the complexity and performance. Normalized BP-based algorithm is chosen as the decoding algorithm by means of theoretic analysis and comparison.2. Compare several LDPC decoder architectures and analyze their advantages and disadvantages. The partial parallel decoder is reaearched for quasi-cyclic LDPC codes. To reduce the decoder’s parallelism degree without losing decodering speed is compromise between the complexity and throughput.3. Study the early stopping methods for iterative decoding algorithm. A simple and reliable early stopping method is given and discussed. The presented early stopping method is applied in the decoder to reduce the decoder power dissipation. The results indicate that the scheme is reliable.4. Design a hardware architecture for the LDPC decoder according to the DTMB system requirements. The working principle of the decoder is discussed in detail. Based on the Verilog hardware design language, the LDPC decoder code is given. Then the decoder’s performance is simulated and illustrated. The simulation results indicate that the hardware decoder BER performance loss is less than0.5dB compared with the float algorithm. The complexity of the decoder is reduced greatly without losing decoding speed.