Design And Impementation Of LDPC Decoder Based On CMMB System

LDPC codes is an error-correcting code with extremely excellent performance, owns to its highly effective decoding algorithm. Also, its decoding is simple, feasible and parallel. It is convenient for hardware implementation. The research on LDPC codes becomes one of the hotspots in channel transmitting field.The China Multimedia Mobile Broadcasting (CMMB) standard, ratified in 2006, is mobile television and multimedia standard developed and specified in China by the State Administration of Radio, Film, and Television (SARFT). LDPC and RS coding is used as part of Forward Error Correcting (FEC) in CMMB system.This paper analyzed in theory, simulated in algorithm, implemented in hardware for LDPC decoder in the demodulator of CMMB transmission system. The paper simulated various decoding algorithms in floating-point model to selected the optimal decoding algorithm and parameters for the system; simulated the Normalized MSA algorithm in fixed-point model to determine the best bits of each variable for the LDPC decoder; by analyzing the structure of LDPC check matrix, under the premise of meeting requirements for CMMB system, designed and implemented the LDPC decoder hardware architecture, which compromised between speed and area.The decoder employs the Normalized MSA algorithm, and Partially Parallel structure for LDPC code in CMMB standard. By fully utilizing the rule of LDPC check matrix, an appropriate architecture and specific method to control memories are proposed, which guarantee high performance and high throughput efficiency, can reuse memories for two different code rates without many hardware resources. It has greatly minished the area, achieves the balance of speed and area. So it has certain practical value, suit for CMMB system. At present, more and more communication system use LDPC code as the channel coding scheme, the architecture in this paper will give a reference to design and implementation of other LDPC decoder.