Research And Design Of High Performance JPEG Encoding And Decoding System

The JPEG compression standard is a lossy intraframe compression standard that is commonly used for compression and encoding of a single static image,and it can provide a restored image with a relatively higher quality.In addition,JPEG can also be employed to process real-time video,so it is widely applied on occasions where video data needs to be processed frame by frame.At the same time,with the rise of the Internet of Things technology,small size and low power consumption have become the constant pursuit of human beings,and the hardware implementation method is more responsive to this trend.Therefore,based on the hardware implementation of ASIC,this paper proposes a high-performance JPEG encoding and decoding system that consists of a high-performance JPEG encoder IP core and a decoder IP core.For the implementation of the encoder IP core in the high-performance JPEG system,this paper provides a new multi-pipeline architecture based on color components,which solves the problem that the DC coefficient cannot be encoded within a single pipeline in the common multi-pipeline architecture;For the Huffman encoding process,The coding method of pipeline level expansion is designed to solve the problem that the Huffman encoding takes too many cycles in the process of encoding complex images.In addition,for the implementation of decoder IP core in high-performance JPEG system,multi-pipeline parallel decoding approch is firstly proposed to substantially improve the JPEG decoding speed.Then,the difficulty of implementation of parallel decoding scheme is analyzed.Based on these,the paper suggests co-design of JPEG encoder and decoder,which means the encoder outputs decoding parameters to assist parallel JPEG decoding.Finally,to restore DC coefficient within a single pipeline,a technique to postpisitively restore IDCT coefficients is proposed.At the final simulation and testing stage,the simulation tool Isim is used to verify the correctness of the design.At the same time,the performance of the actual circuit of the JPEG system is tested based on Xilinx Spartan-6(XC6SLX100)FPGA platform.At a system clock frequency of 148.5 MHz,the encoder IP core can achieve a stable encoding rate of 61.99 frames per second,while the decoding speed of the decoder varies from image to image,but is stablely above 52.60 frames per second.Compared with the design in other literatures,the encoder and decoder IP core in the JPEG system not only have high encoding and decoding capability,but also maintain a good balance between performance and resource consumption.